System console - MSP430

Last updated : 06/25/2008

In this page, we will discuss about programming (flashing) a Texas Instrument MSP430F135 microcontroller, using MSP430 BSL (BootStrap Loader ) feature and the Altera system console tool, available in the latest Quartus version (8.0 at this time).

The purpose of this page is to describe how it is possible to access BSL capability from your PC, using the Altera system console tool,TCL scripts and an Altera JTAG probe (USB-Blaster for example).

• Hardware part (schematic): 
  

   Note that FPGAs  I/Os should reside in 3.3V powered bank, as the MSP430 is powered from a +3.3V source.

--------------------                  -------------------
MSP430F135         |		      | FPGA
                   | P1.1/TX          |  --------------
	pin 13   ->|------------------|->|            |
                   | P2.2/RX          |  | FIFOed UART|
	pin 22   <-|------------------|<-|            | 
                   |                  |  --------------
                   | TCK              |  --------
	pin 57   <-|------------------|<-|      |
                   | RESET            |  | PIO  |       
	pin 58   <-|------------------|<-|      |   
                   |                  |   -------
--------------------                  --------------------

In BSL mode and from an MSP430F135 point of view,

• P1.1 is used as RS232 TX output
• P2.2 is used as RS232 RX input 
• TCK (normally JTAG pin) become 'TEST' input. Note that on some other MSP430, there is a dedicated pin (TEST) instead of TCK. For the MSP430F135, TCK act as TEST pins.
• RESET : MSP430 reset input.
  

From an FPGA point of view, the RESET pin should be an open-drain pull-uped output, as the RESET line may be connected to an other device (reset controller in particular). Note that voltage level are 3.3V and not RS232 higher voltage level. Excepted that, communication format is a standard RS format : 9600 bauds, 8 bits, even parity and 1 stop bits.
 

• System level and software aspects :

• SOPC builder

You must build an SOPC system with at least the following components :

- Altera JTAG to Avalon Master Bridge   : provided by Altera, requires Quartus 8.0. 
- Altera PIO (Parallel I/O)                        : provided by Altera. Suggested base adress is 0x00811040, as it is the default value hard-coded in my script. Only 2 bits are required, configured as output only and no irq.
- FIFOed UART (RS-232 serial port)7.1 : made by longshot and available on Nios Forum . This is a slightly modified version of the standard Altera UART, in order to include RX and TX FIFOs. The RX FIFO is mandatory to avoid data loss when receiving data from MSP430. Suggested base address is 0x00000000, as it is the default value hard-coded in my TCL script. By default, UART is configured as 9600 bauds, 8 bits, even parity and 1 stop bits with 256 bytes RX and TX FIFOs, no CTS/RTS lines.

Here is a screenshot of my system, targeted for an Arrow LPRP Cyclone III board (see notes below) :

It includes a NIOS processor, a JTAG to Avalon bridge, a PIO, a FIFOed UART, a clock domain bridge and a PLL. The clock domain bridge is needed to run the FIFOed UART at 48MHz and some other components at a higher frequency (96 MHz). There is a bug in the FIFOed UART so that you must use a near 50 MHz input clock, otherwise baud rates will be false. As a workaround, I used a clock crossing bridge.

• Software files

The project consist of the following files (see attachments) :

• FIFOed avalon uart.zip : FIFOed UART IP. Unzip content somewhere, then tell SOPC builder about the path to this IP(in SOPC Builder, menu Tools->Options->'IP search path').
  
• bsl.qar : SOPC builder and Quartus archived project. Contains Quartus settings as well as SOPC builder system files (.ptf, .sopc, .sopcinfo ...). Generated with Quartus 8.0. Pinout targets an Arrow LPRP board. Do **not** restore archived project to a target directory name containing space(s), otherwise you will run into weird problems during generation and compilation. Also note that before compiling Quartus project, you will have to launch SOPC Builder and regenerate the system. This is required because some path are hardcoded in the .qip file (Quartus IP file), therefore they might not match your local installation. The top design file is top_bsl.vhd, which instantiante the SOPC design and connect BSL pins to the UART and PIO components. The 4 BSL pins are also connected to the 4 user LEDs available on the LPRP board in order to monitor BSL lines activity.
  
• bsl430.tcl : a TCL script which allows reading data from a Motorolas S-REC file and write them to MSP430. Comments in source should be sufficient to understand how it works. To launch the script, type source <install_path>/bsl430.tcl in the Altera system console, where <install-path> is the path to the TCL script. 
  
• test_f135.s19 : S-REC binary file (code) for test purpose. Generated using HEX430.exe utility from the "Code Composer Essentials" suite. I used the following command line : hex430.exe -m3 "object_file" -o "srec_file.s19" -order MS -romwidth 16
  
• main.c : C source file of test_f135.s19 code file. Compiled using Texas Instrument "Code Composer Essentials for MSP430 version 2.0.5.0"  development suite.

The bsl430.tcl TCL script performs the following things:

- enter BSL mode
- patch BSL code. Required, because MSP430F135 has version 1.1 of BSL, which is bugged !
- write a Motorola S-REC file into MSP430F135. S-REC file can contain data addressing indifferently flash or RAM, or even MSP430 registers. Beware not to overwrite the RAM data needed by the BSL firmware, otherwise BSL will crash and programming will fail.
- at the end of programming, the MSP430 exit BSL mode and start user code by applying a reset strobe.

• TCL script usage
  

To use this script, you must launch the Altera system console from an Altera command shell : system-console -cli
The -cli option is recommended, otherwise messages are not displayed in real time on you screen.
Currently, path to S-REC is hard-coded (line set srec_file "D:/User/Projet/msp430/work/test_f135/Debug/test_f135.s19"), and you will have to change path to the .s19 file to your local path.
The S-REC parser currently support only S0,S3 and S7 record field. Moreover, due to BSL limitations, an S3 record field must have a maximum of 240 data bytes.

Here is a screenshot of the system-console output:

--------------------------------------------------------------
 MSP430F135 - BSL programmer.

 (c) 2008/06 I. GEHIN
--------------------------------------------------------------


Initializing JTAG services...
Successfully opened JTAG service '/root/connections/USB-Blaster [USB-0]/EP3C25/[
MFG:70 ID:34 INST:0 VER:6]'.
Processor has been reset
Processor has been stopped
Entering BSL mode...
Resetting MSP430 (hardware reset) ...
MSP430 should be in BSL mode.
Executing 'Mass erase' command (will clear FLASH and reset password) ...
(debug info) command result : 0x90
(debug info) Applying BSL 1.1 patch' ...
(debug info) 'RX password' result : 0x90
(debug info) 'LOAD PC' result : 0x90
(debug info) 'RX password' result : 0x90
(debug info) ----------- PATCHING BSL ... ---------------
(debug info) 'RX DATA BLOCK' result : 0x90
(debug info) ----------- PROGRAMMING MSP430 ---------------

===============================================================================
** Writing SREC file 'D:/User/Projet/msp430/work/test_f135/Debug/test_f135.s19'

** WRITE : 0xC000 : '0x0A 0x12 0x09 0x12 0x0D 0x4C 0x3D 0x93 0x10 0x24 0x0C 0x3C
 0x8F 0x12 0x2A 0x53 0x10 0x3C 0x3C 0x4D 0x09 0x4D 0x0E 0x4A 0xB0 0x12 0xCA 0xC0
 0x09 0x5A'
 ** READ : 0xC000 : '0x0a 0x12 0x09 0x12 0x0d 0x4c 0x3d 0x93 0x10 0x24 0x0c 0x3c
 0x8f 0x12 0x2a 0x53 0x10 0x3c 0x3c 0x4d 0x09 0x4d 0x0e 0x4a 0xb0 0x12 0xca 0xc0
 0x09 0x5a'
** WRITE : 0xC01E : '0x0D 0x49 0x1D 0x53 0x1D 0xC3 0x3A 0x4D 0x0A 0x93 0xF4 0x23
 0x3A 0x40 0xFF 0xFF 0x3A 0x93 0x03 0x24 0x2F 0x4A 0x0F 0x93 0xEA 0x23 0x30 0x40
 0xE6 0xC0'
 ** READ : 0xC01E : '0x0d 0x49 0x1d 0x53 0x1d 0xc3 0x3a 0x4d 0x0a 0x93 0xf4 0x23
 0x3a 0x40 0xff 0xff 0x3a 0x93 0x03 0x24 0x2f 0x4a 0x0f 0x93 0xea 0x23 0x30 0x40
 0xe6 0xc0'
** WRITE : 0xC03C : '0x3E 0x40 0xFF 0xFF 0x3F 0x40 0xFF 0xFF 0x3F 0x93 0x05 0x20
 0x3E 0x93 0x03 0x20 0x0C 0x43 0x0D 0x43 0x05 0x3C 0x1C 0x42 0xFF 0xFF 0x2D 0x43
 0x3D 0x50'
 ** READ : 0xC03C : '0x3e 0x40 0xff 0xff 0x3f 0x40 0xff 0xff 0x3f 0x93 0x05 0x20
 0x3e 0x93 0x03 0x20 0x0c 0x43 0x0d 0x43 0x05 0x3c 0x1c 0x42 0xff 0xff 0x2d 0x43
 0x3d 0x50'
** WRITE : 0xC05A : '0xFF 0xFF 0xB0 0x12 0x88 0xC0 0x30 0x41 0x03 0x43 0xFF 0x3F
 0x92 0x12 0x00 0x02 0x1F 0x42 0x06 0x02 0x0F 0x93 0x01 0x24 0x8F 0x12 0x1F 0x42
 0x04 0x02'
 ** READ : 0xC05A : '0xff 0xff 0xb0 0x12 0x88 0xc0 0x30 0x41 0x03 0x43 0xff 0x3f
 0x92 0x12 0x00 0x02 0x1f 0x42 0x06 0x02 0x0f 0x93 0x01 0x24 0x8f 0x12 0x1f 0x42
 0x04 0x02'
** WRITE : 0xC078 : '0x0F 0x93 0x01 0x24 0x8F 0x12 0x92 0x12 0x02 0x02 0xB0 0x12
 0x62 0xC0 0xFF 0x3F 0x21 0x83 0xB2 0x40 0x80 0x5A 0x20 0x01 0xE2 0xD3 0x22 0x00
 0xE2 0xE3'
 ** READ : 0xC078 : '0x0f 0x93 0x01 0x24 0x8f 0x12 0x92 0x12 0x02 0x02 0xb0 0x12
 0x62 0xc0 0xff 0x3f 0x21 0x83 0xb2 0x40 0x80 0x5a 0x20 0x01 0xe2 0xd3 0x22 0x00
 0xe2 0xe3'
** WRITE : 0xC096 : '0x21 0x00 0xB1 0x40 0x10 0x27 0x00 0x00 0x91 0x83 0x00 0x00
 0x81 0x93 0x00 0x00 0xFB 0x23 0xF5 0x3F 0x31 0x40 0x00 0x04 0xB0 0x12 0xFA 0xC0
 0x0C 0x93'
 ** READ : 0xC096 : '0x21 0x00 0xb1 0x40 0x10 0x27 0x00 0x00 0x91 0x83 0x00 0x00
 0x81 0x93 0x00 0x00 0xfb 0x23 0xf5 0x3f 0x31 0x40 0x00 0x04 0xb0 0x12 0xfa 0xc0
 0x0c 0x93'
** WRITE : 0xC0B4 : '0x04 0x24 0x3C 0x40 0xFE 0xC0 0xB0 0x12 0x00 0xC0 0xB0 0x12
 0x3C 0xC0 0x1C 0x43 0xB0 0x12 0x66 0xC0 0xFF 0x3F 0x0F 0x4C 0x0E 0x93 0x05 0x24
 0x1F 0x53'
 ** READ : 0xC0B4 : '0x04 0x24 0x3c 0x40 0xfe 0xc0 0xb0 0x12 0x00 0xc0 0xb0 0x12
 0x3c 0xc0 0x1c 0x43 0xb0 0x12 0x66 0xc0 0xff 0x3f 0x0f 0x4c 0x0e 0x93 0x05 0x24
 0x1f 0x53'
** WRITE : 0xC0D2 : '0xFF 0x4D 0xFF 0xFF 0x1E 0x83 0xFB 0x23 0x30 0x41 0x34 0x41
 0x35 0x41 0x36 0x41 0x37 0x41 0x38 0x41 0x39 0x41 0x3A 0x41 0x30 0x41 0x82 0x4C
 0x02 0x02'
 ** READ : 0xC0D2 : '0xff 0x4d 0xff 0xff 0x1e 0x83 0xfb 0x23 0x30 0x41 0x34 0x41
 0x35 0x41 0x36 0x41 0x37 0x41 0x38 0x41 0x39 0x41 0x3a 0x41 0x30 0x41 0x82 0x4c
 0x02 0x02'
** WRITE : 0xC0F0 : '0x30 0x41 0x82 0x4C 0x00 0x02 0x30 0x41 0x30 0x41 0x1C 0x43
 0x30 0x41'
 ** READ : 0xC0F0 : '0x30 0x41 0x82 0x4c 0x00 0x02 0x30 0x41 0x30 0x41 0x1c 0x43
 0x30 0x41'
** WRITE : 0xC0FE : '0x02 0x00 0x00 0x02 0xF8 0xC0 0x02 0x00 0x02 0x02 0xF8 0xC0
 0x02 0x00 0x04 0x02 0x00 0x00 0x02 0x00 0x06 0x02 0x00 0x00 0x00 0x00'
 ** READ : 0xC0FE : '0x02 0x00 0x00 0x02 0xf8 0xc0 0x02 0x00 0x02 0x02 0xf8 0xc0
 0x02 0x00 0x04 0x02 0x00 0x00 0x02 0x00 0x06 0x02 0x00 0x00 0x00 0x00'
** WRITE : 0xFFFE : '0xAA 0xC0'
 ** READ : 0xFFFE : '0xaa 0xc0'
*** Total Elapsed time : 6 s.
(debug info) ----------- RESETTING MSP430 ----------------

Closing jtag service.
%

• The design was tested on an LPRP board, available from Arrow. However, it should be quite easy to port this design to any board.
• The design targets an MSP430F135 device. However, it should be quite easy to support any other MSP430 device supporting BSL features.
• I'm not a code guru and this is my first TCL script, so there are probably many rooms for code clean-up or optimizations. But it works.
• The script implements a sub-set of BSL commands, i.e only those needed to program part.
  

• Implement command line parser.
• Improve error handling management.
• Add support for more BSL command.
• Tests more MSP430 devices. Next one planned is MSP430F2111.
  

• Texas Instruments app note SLAA089D.pdf  (see attachments)

     "Application Report
     SLAA089D–December 1999–Revised August 2006
     Features of the MSP430 Bootstrap Loader"

•  Texas Instruments app note SLA0096D.pdf (see attachments)

    "Application Report
    SLAA096D–September 2005–Revised August 2006
    Application of Bootstrap Loader in MSP430
    With Flash Hardware and Software Proposal"